`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: WuHan University
// Engineer: Leequo94
// 
// Create Date: 2018/09/13 
// Design Name: 
// Module Name: max_filter2x2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// input sequence: 
// s_axis_tvald : ______|``````````.........``````````|________
// s_axis_tdata : ______|XXXXXXXXXX.........XXXXXXXXXX|________
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module max_filter2x2 # 
( 
    parameter   COL = 1920,
    parameter   ROW = 1080
)
(
    input       wire            clk,
    input       wire            rst_n,
    input       wire            s_axis_tvald,
    input       wire    [7:0]   s_axis_tdata,
    output      wire            m_axis_tvald,
    output      wire    [7:0]   m_axis_tdata
);
////////////////////////////////////////////////////////////////////////////////
wire m_aixs_shift_fifo_tvald;
wire [7:0] m_aixs_shift_fifo_tdata0;
wire [7:0] m_aixs_shift_fifo_tdata1;
////////////////////////////////////////////////////////////////////////////////
shift_fifo2line # 
( 
    .COL ( COL ),
    .ROW ( ROW )
) shift_fifo2line_inst 
(
    .clk             ( clk                      ), // input       wire            
    .rst_n           ( rst_n                    ), // input       wire            
    .s_axis_tvald    ( s_axis_tvald             ), // input       wire            
    .s_axis_tdata    ( s_axis_tdata             ), // input       wire    [7:0]   
    .m_axis_tvald    ( m_aixs_shift_fifo_tvald  ), // output      wire            
    .m_axis_tdata0   ( m_aixs_shift_fifo_tdata0 ), // output      wire    [7:0]   
    .m_axis_tdata1   ( m_aixs_shift_fifo_tdata1 )  // output      wire    [7:0]   
);
////////////////////////////////////////////////////////////////////////////////
reg [7:0] line1_pix_d1;
reg [7:0] line2_pix_d1;
reg m_aixs_shift_fifo_tvald_d0;
always @ (posedge clk,negedge rst_n)
begin 
    if (!rst_n) begin 
        line1_pix_d1 <= 8'd0;
        line2_pix_d1 <= 8'd0;
        m_aixs_shift_fifo_tvald_d0 <= 1'd0;
    end 
    else begin 
        line1_pix_d1 <= m_aixs_shift_fifo_tdata0;
        line2_pix_d1 <= m_aixs_shift_fifo_tdata1;
        m_aixs_shift_fifo_tvald_d0 <= m_aixs_shift_fifo_tvald;
    end 
end 
////////////////////////////////////////////////////////////////////////////////
// compared pix value 
wire pix_en = m_aixs_shift_fifo_tvald_d0 & m_aixs_shift_fifo_tvald;
reg [7:0] pix_max;
wire [7:0] line1_pix = m_aixs_shift_fifo_tdata0;
wire [7:0] line2_pix = m_aixs_shift_fifo_tdata1;
always @ (posedge clk,negedge rst_n)
begin 
    if (!rst_n) begin 
        pix_max <= 8'd0;
    end 
    else if (pix_en) begin 
        if (line1_pix_d1 >= line1_pix && line1_pix_d1 >= line2_pix && line1_pix_d1 >= line2_pix_d1 ) begin
            pix_max <= line1_pix_d1;
        end 
        else if (line1_pix >= line1_pix_d1 && line1_pix >= line2_pix && line1_pix >= line2_pix_d1 ) begin
            pix_max <= line1_pix;
        end 
        else if (line2_pix_d1 >= line1_pix_d1 && line2_pix_d1 >= line2_pix && line2_pix_d1 >= line1_pix ) begin
            pix_max <= line2_pix_d1;
        end 
        else if (line2_pix >= line1_pix_d1 && line2_pix >= line1_pix && line2_pix >= line2_pix_d1 ) begin
            pix_max <= line2_pix;
        end 
        else begin 
            pix_max <= line2_pix;
        end 
    end 
    else begin 
        pix_max <= line2_pix;
    end 
end 
////////////////////////////////////////////////////////////////////////////////
reg m_axis_tvald_reg;
always @ (posedge clk,negedge rst_n)
begin 
    if (!rst_n) begin 
        m_axis_tvald_reg <= 1'd0;
    end 
    else begin 
        m_axis_tvald_reg <= pix_en;
    end 
end 
assign m_axis_tdata = pix_max;
assign m_axis_tvald = m_axis_tvald_reg;

endmodule 